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TC90A53N/F
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
TC90A53N,TC90A53F
3-LINE DIGITAL Y / C SEPARATOR IC
TC90A53N / F is a 3-line digital Y / C separator IC which separates luminance signal Y and chroma signal C from composite video signals. Toshiba's logical comb filter realizes good Y / C separation at low cost.
FEATURES
* TV format : NTSC (3.58) * Dynamic comb filter * Vertical edge enhancement circuit * PLL 4 x multiplier circuit * Internal 8-bit 4 fsc AD converter * Internal 8-bit 4 fsc DA converter (2 ch) * 1-line color dot interference reducer circuit * Sync tip clamp circuit * Internal 2H-line memory * Color killer mode (Y / C separation off) * Chroma signal C output wide band mode * Package : SDIP 28-pin and SOP 28-pin * 5 V single power supply
Weight: SDIP28-P-400-1.78: 1.7 g (Typ.) SOP28-P-450-1.27: 0.8 g (Typ.)
000707EBA1
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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BLOCK DIAGRAM
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PIN CONNECTION
PIN FUNCTION
PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIN NAME VREFL VSS1 VDD1 VREFH ADIN BIAS1 CLAMPC TEST1 1 / 2 VDD VFIL CKIN VDD2 VSS2 KILLER ADC Bias ADC GND ADC Power Supply ADC Bias Video Signal Input ADC Bias Clamp Circuit Filter Test Pin Line Memory Bias VCO Filter Clock Input PLL Power Supply PLL GND L : Color Mode H : Black And White Mode FUNCTION PIN No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PIN NAME CBPF VENH0 VENH1 1LINE CORING VDD3 VSS3 BIAS3 COUT BIAS2 YOUT VREF1 VDD4 VSS4 FUNCTION L : C-BPF = Wide Band H : Narrow Band Sets Vertical Enhance Amount. (VENH0, VENH1) = (L, L) = Small (H, L) = Small (L, H) = Medium, (H, H) = Large L : 1-line Color ON H : 1-line Color OFF L : Coring ON (2LSB) H : Coring OFF (0LSB) Digital Power Supply Digital GND DAC Bias C Output DAC Bias Y Output DAC Bias DAC Power Supply DAC GND
(Note) : Pins 9 and 26 need external bias.
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PIN FUNCTION
PIN No. PIN NAME FUNCTION I/O INTERFACE
1
VREFL
ADC bias pin. Sets lower limit of range D for ADC. Fixed internally to 1.5 V (typ.). Connect 0.01 mF capacitor between this pin and GND.
3/4
2 3
VSS1 VDD1
ADC GND ADC power supply (+5 V)
3/4 3/4
3/4 3/4
4
VREFH
ADC bias pin. Sets upper limit of range D for ADC. Fixed internally to 3.5 V (typ.). Connect 0.01 mF capacitor between this pin and GND.
3/4
5
ADIN
Composite video signal input pin.
I
6
BIAS1
ADC bias pin. Fixed internally to 1.3 V (typ.). Connect 0.01 mF capacitor between this pin and GND.
3/4
7
CLAMPC
External filter used for Sync tip clamping the input composite video signal. Connect 510 kW and 4700 pF between this pin and GND.
3/4
8
TEST
Test pin. Connect GND.
3/4
3/4
9
1 / 2 VDD
Line-memory bias. Supply 1 / 2 VDD by dividing digital power supply using a resistor. Connect 0.01 mF capacitor between this pin and GND.
I
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PIN No. PIN NAME FUNCTION I/O INTERFACE
10
VFIL
Connect a VCO filter.
3/4
11
CKIN
Inputs clock. First DC-cut fsc clock in sync with color burst using a capacitor, then input the result.
I
12 13
VDD2 VSS2
PLL power supply (+5 V) PLL GND
3/4 3/4
3/4 3/4
14
KILLER
Selects color killer mode. L : Color mode H : Black and white mode (Y / C sep off)
I
15
CBPF
Selects color signal horizontal band. L : Wide band (does not pass BPF) H : Narrow band (passes BPF)
I
Select vertical enhance amount. VENH0 VENH1 16 17 VENH0 VENH1 L H L H L : Small (+0.25) L : Small (+0.25) H : Medium (+0.75) H : Large (+1.25) I
18
1 LINE
1-line color dot interference reducer ON / OFF L : 1-line color dot interference reducer ON H : 1-line color dot interference reducer OFF
I
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PIN No. PIN NAME FUNCTION I/O INTERFACE
Selects coring. 19 CORING L : Coring ON (2LSB) H : Coring OFF (0LSB) I
20 21
VDD3 VSS3
Digital power supply (+5 V) Digital GND
3/4 3/4
3/4 3/4
22
BIAS3
DAC bias pin. Fixed internally to 3.5 V (typ.). Connect a 0.01 mF capacitor between this pin and GND.
3/4
23
COUT
Outputs C signal.
O
24
BIAS2
DAC bias pin. Fixed internally to 1.6 V (typ.). Connect a 0.01 mF capacitor between this pin and GND.
3/4
25
YOUT
Outputs Y signal.
O
26
VREF1
DAC bias pin. Sets lower limit of range D for DAC. Supply power by dividing power for DAC using a resistor. Recommended value : 3.0 V
I
27 28
VDD4 VSS4
DAC power supply (+5 V) DAC GND
3/4 3/4
3/4 3/4
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DESCRIPTION OF FUNCTIONS
(1) CLAMP (Input clamp) Circuit used to Sync tip clamp composite signal. Apply feedback clamp so that at Y / C separation, the minimum data value after A / D conversion is the internally-fixed level. (2) ADC (A / D converter) High-speed series-parallel 8-bit A / D converter (Dynamic Range: 2.0V). Input composite video signal with amplitude of 1.5 Vp-p (sync to white 100%). (3) 1 H memory Line memory consisting of DRAM for 1 H delay. Two line memories configure a 3-line comb filter. Because the system clock is 4 fsc (14.3 MHz), 910 clocks / 1 H is set. (4) VENH (Vertical enhancer circuit) After coring (2LSB) the non-correlation component among the three lines of the luminance signal, this block enhances the vertical outline. The enhance amount can be selected from three settings : large (+1.25), medium (+0.75), and small (+0.25). The vertical enhance amount is added to the luminous signal obtained by subtracting the color signal from the composite signal, then the luminous signal is output via the D / A converter. Note that if the luminous signal is lower than the pedestal level (internally-fixed value), the vertical enhance amount is not added to. (5) BPF (Horizontal bandpass filter) Uses fsc as the center frequency. Filters the composite signal delayed by 0 H, 1 H, or 2 H and extracts the color signal. The bandpass filter for outputting the color signal at a later stage can be switched on or off to select output of a narrow- or wide-band color signal. (6) DCF (Vertical dynamic comb filter) Vertical bandpass filter which extracts the color signal by detecting vertical non-correlation. Using Toshiba logic, determines the correlation among three lines. If no correlation, determines as the luminous signal and suppresses output of the color signal. (7) 1-line color dot interference reducer circuit Improves color dot interference on a screen where only 1 line has color so that the C signal is processed as the Y signal. Extracts 1-line color dot component and the result is added to the output from the dynamic comb filter. (8) RTIM (Clock / memory timing generator) This block supplies x 4 fsc (14.3 MHz) obtained using the VCO via a buffer to the blocks and generates the timing signal necessary for memory. (9) PLL (x 4 clock generator) Multiplies fsc (3.58 MHz) by 4 and generates system clock 4 fsc (14.3 MHz). (10) DAC (D / A converter) High-speed 8-bit D / A converter. The output amplitudes are : Y output of 1.5 V p-p (typ.) and C output at burst level of 572 mV p-p (typ.). (11) Color killer circuit When the input video signal is a monochrome image, this circuit enables effective use of the luminance signal information regardless of whether there is a burst signal. It does this by preventing the chroma signal output from the comb filter from being subtracted from the luminance signal. While the VBI signal is active it is better not to use the comb function. Setting the KILLER pin to High at this time enables the use of character multiplex and other signals from the Y output unchanged. But since Vertical edge enhancement does not become OFF, be careful when using with Vertical edge enhancement.
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MODE LIST
PIN14 KILLE R L H 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 PIN15 CBPF 3/4 3/4 L H 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 PIN16 VENH0 3/4 3/4 3/4 3/4 L H L H 3/4 3/4 PIN17 VENH1 3/4 3/4 3/4 3/4 L L H H 3/4 3/4 PIN18 1 LINE 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 L H 3/4 3/4 PIN19 CORING 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 L H MODE Y / C separation ON Y / C separation OFF Color signal horizontal band, wide Color signal horizontal band, narrow Vertical enhance small Vertical enhance small Vertical enhance medium Vertical enhance large 1-line color ON 1-line color OFF Coring ON Coring OFF Color mode Black and white mode (killer) Does not pass BPF for color signal output. Passes BPF for color signal output. Enhance amount : (+0.25) Enhance amount : (+0.25) Enhance amount : (+0.75) Enhance amount : (+1.25) 1-line color dot interference reducer circuit ON 1-line color dot interference reducer circuit OFF Coring circuit ON (2LSB) Coring circuit OFF (0LSB) OPERATION
3/4
3/4
3/4
3/4
MAXIMUM RATINGS (Ta = 25C)
CHARACTERISTIC Power Supply Voltage Input Voltage Power Dissipation Storage Temperature TC90A53N TC90A53F SYMBOL VDD VIN PD (Note) Tstg RATING VSS~VSS + 6.0 -0.3~VDD + 0.3 900 600 -55~125 UNIT V V mW C
(Note) : Ta = 75C
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTIC Power Supply Voltage Input Voltage Operating Temperature SYMBOL VDD VIN Topr TEST CONDITION 3/4 3/4 3/4 MIN 4.75 0 -10 TYP. 5.0 3/4 3/4 MAX 5.25 VDD 75 UNIT V V C
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ELECTRICAL CHARACTERISTICS DC CHARACTERISTICS (Ta = 25C, VDD = 5 V)
CHARACTERISTIC Operating Voltage Operating Current Output Voltage Level SYMBOL VDD IDD YOUT COUT VREFL VREFH ADIN BIAS1 Pin Voltage Level BIAS2 BIAS3 CLAMPC VFIL CKIN Input Voltage High Level Low Level VIH VIL CIN RPD 1 1 1 1 1 CLOCK = 3.579545 MHz 500 mVp-p VREF1 = 3.0 V 1 / 2 VDD = 2.5 V VIN = No input (Note 1) TEST CIRCUIT 1 1 1 TEST CONDITION MIN 4.75 40 3.0 3.9 1.4 3.4 1.5 0.8 0.8 2.4 2.0 0.9 1.5 4 3/4 3/4 25 TYP. 5.0 60 3.15 4.0 1.5 3.5 1.6 1.4 1.6 3.4 3.0 1.9 2.2 3/4 3/4 50 50 MAX 5.25 80 3.3 4.1 1.6 3.6 1.8 2.4 2.6 4.4 4.0 2.9 3.0 3/4 1 3/4 100 V V pF k V UNIT V mA V
ADIN Pin Input Capacitance Pull-Down Resistance
(Note 1) : Pins 9 and 26 need external bias.
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AC CHARACTERISTICS Y output (Ta = 25C, VDD = 5 V, clock frequency = 3.579545 MHz, 0.5 Vp-p, S1 = 2, VREF1 =
3.0 V)
TEST CIRCUIT 1 1 1 1
CHARACTERISTIC Input Level Low-Frequency Gain
SYMBOL VIN GV MTF1
TEST CONDITION 0~140 IRE ( Figure 2 ) S2 = 2, S3 = 2, S4 = 1, S5 = 2 VIN = 15.734 kHz, 1.5 Vp-p Vdc = 2.5 V S2 = 2, S3 = 2, S4 = 1, S5 = 2 VIN = 1.5 Vp-p Vdc = 2.5 V S2 = 2, S3 = 2, S4 = 1, S5 = 2 VIN = 1.5 Vp-p Vdc = 2.5 V S2 = 1, S3 = 1, S4 = 1, S5 = 2 VIN = 5-stage staircase waveform, 1.5Vp-p (Figure 2) S2 = 1, S3 = 1, S5 = 2 VIN = 15.734 kHz, 1.5 Vp-p Vdc = 2.5 V V1 V2 Zo = 400 V2 V1 : S4 = 1, V2 : S4 = 2 f2 / f1 f4 / f1
MIN 3/4 -0.5 -2.0 -3.0
TYP. 1.5 0.0 -1.2 -2.0
MAX 1.6 0.5 -0.5 -1.5
UNIT Vp-p dB
Frequency Characteristics
MTF2
dB
Comb Characteristics
Comb
1
f2 / f3
40
45
3/4
dB
Ls Linearity (Figure 1) Ly
1
Y1 / Y2
35
40
43 %
1
S / Y2
57
60
63
Output Impedance
Zo
1
250
400
700
W
Clock Leakage (4 fsc component) Clock Dominant Wave Leakag (fsc component)
Lck
1
S2 = 2, S3 = 2, S4 = 1, S5 = 1 VIN = No input S2 = 2, S3 = 2, S4 = 1, S5 = 1 VIN = No input
3/4
5.0
20
mVrms
Lsc
1
3/4
1.0
2.0
mVrms
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3.0 V)
C output (Ta = 25C, VDD = 5 V, clock frequency = 3.579545 MHz, 0.5 Vp-p, S1 = 1, VREF1 =
CHARACTERISTIC SYMBOL TEST CIRCUIT 1 TEST CONDITION Amplitude difference between fsc where S2 = 2, S3 = 2, S4 = 1, S5 = 2 and fsc - 503496 Hz VIN = 1.5 Vp-p, Vdc = 2.5 V Amplitude difference between fsc where S2 = 2, S3 = 2, S4 = 1, S5 = 2 and fsc - 503496 Hz VIN = 1.5 Vp-p, Vdc = 2.5 V S2 = 2, S3 = 2, S4 = 1, S5 = 1, VIN = fsc, 430 mVp-p S2 = 2, S3 = 2, S4 = 1, S5 = 2 VIN = 430 mVp-p, Vdc = 2.5 V MIN TYP. MAX UNIT
Wide Band BPF Characteristics Narrow Band
BWCW
-0.5
-0.2
3/4 dB
BWCN
1
-1.0
-0.5
3/4
Gain
CV
1
-2
-0.9
-0.6
dB
Comb Characteristics
Comb
1
f3 / f2
30
35
3/4
dB
Differential Gain
DG
1
Differential Phase
DP
1
S2 = 2, S3 = 3, S4 = 1, S5 = 1, VIN = 5-stage staircase waveform, Y = 140 IRE = 1.5 Vp-p C = 40 IRE (Figure 2) DG = (Comax-Comin) / Comax (Figure 3) S2 = 2, S3 = 2, S5 = 2 VIN = 15.734 kHz, 1.5 Vp-p Vdc = 2.5 V V1 V2 Zo = 400 V2 V1:S4 = 1, V2:S4 = 2
0
2
5
%
0
2
5
Output Impedance
Zo
1
250
400
700
Clock Leakage (4 fsc Component) Clock Dominant Wave Leakag (fsc Component)
Lck
1
S2 = 2, S3 = 2, S4 = 1, S5 = 1, VIN = No input S2 = 2, S3 = 2, S4 = 1, S5 = 1, VIN = No input
3/4
5.0
20
mVrms
Lsc
1
3/4
0.3
1.0
mVrms
f1 = 15.734 kHz f2 = 3.587412 MHz f3 = 3.595279 MHz f4 = 4.783216 MHz
CLOCK PLL CIRCUIT CHARACTERISTICS
CHARACTERISTIC Pull-in Frequency Range (4 fsc Component) Input Amplitude (fsc Component) SYMBOL TEST CIRCUIT 1 TEST CONDITION MIN TYP. MAX UNIT
fck
3/4
3.57
3.58
3.59
MHz
Vck
1
3/4
0.4
3/4
3/4
Vp-p
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TEST CIRCUIT 1
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LINEARITY TEST (Figure 1) 5-STAGE STAIRCASE SIGNAL (Figure 2)
CHROMA DIFFERENTIAL GAIN (Figure 3)
REFERENCE DATA (Figure 4-a) DEFINITION OF VERTICAL ENHANCE
a : Vertical edge level
b : enhancement level
Note that output does not drop below the pedestal level (64 / 256) due to vertical outline enhance.
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(Flgure 4-b) VERTICAL ENHANCE CHARACTERISTICS
(Figure 4-c) VERTICAL ENHANCE CHARACTERISTICS(ENLARGED)
(Figure 5) FREQUENCY CHARACTERISTICS OF COLOR SIGNAL OUTPUT
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APPLICATION CIRCUIT
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PACKAGE DIMENSIONS
SDIP28-P-400-1.78 Unit : mm
Weight : 1.7 g (Typ.)
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PACKAGE DIMENSIONS
SOP28-P-450-1.27 Unit : mm
Weight : 0.8 g (Typ.)
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